1. Field of the Invention
The present invention relates to a method for producing compound semiconductor single crystal substrates adapted for semiconductor devices. More particularly, the present invention relates to a method available for growing III-V group compound semiconductor single crystals such as GaAs, GaP, InAs, InP and so on, and a method for heat-treating the grown compound semiconductor single crystals.
2. Description of the Prior Art
Various methods for producing compound semiconductor single crystals are well known. For example, a seed crystal is immersed in the melted solution of the crystal in a crucible and then the seed crystal is pulled up being rotated relatively to the crucible to grow the single crystal from the seed crystal. As an alternative method, the melted solution is gradually solidified to grow the single crystal. In industrial scale, Liquid Encapsulated Czochralski Method (LEC Method) which belongs to the former method, and Gradient Freeze Method (GF Method), Horizontal Bridgeman Method (HB Method), and Vertical Bridgeman Method (VB Method), belongs to the latter method and all are well known.
Although these single crystal growth methods each is a little different from each other, it is possible to grow crystals with a basically similar process that the temperature gradient between the crystal and the melted solution is formed to solidify gradually the melted solution.
In the process, while the interface between the liquid and the solid where the crystal is grown is kept at its melting point, the crystal part already grown is kept at lower temperatures than the melting point. Accordingly, these single crystal growth methods do not avoid producing single crystals whose properties are inhomogeneous.
Therefore, if the wafers cut from the compound semiconductor single crystals grown by the above described methods are used for the substrates of electronic devices, the yield in such electronic device manufactures will become poor because of the variations in electrical properties across the wafer. For example, even though the wafers cut from undoped or Cr-doped GaAs single crystals have been used as the substrates for specific electronic devices such as ion-implanted type FETs, the above described variations across the wafer will cause variations in threshold voltage Vth of many FETs formed on the wafer.
Conventionally, in order to reduce the variation in the electrical properties across the wafer, Rumsby has provided the method, named "ingot annealing method" for annealing the single crystal ingot in an evacuated quartz ampoule at a high temperature from 620.degree. to 1000.degree. C. Refer to "D. Rumsby, R. M. Ware, B. Smith, M. Tyjberg, M. R. Brozel and E. J. Foulkes GaAs IC Symposium, Phoenix, Technical Digest (1983)34-37". Thereafter, various ingot annealing methods have been provided such as Japanese Patent Application Laid-Open Publications No. 61-201700, No. 61-222999, No. 62-21699, No. 62-21800, and No. 62-162700.
While such conventional ingot annealing methods can reduce the variations of resistivity and mobility across the wafer and therefore a homogeneous photoluminescence image can be obtained across the wafer, the wafer produced by such methods can not sufficiently reduce the variation in the threshold voltage, Vth, across the wafer used as the substrates for FETs.
The inventors of the present invention have attempted various heat-treatments and have taken note of a cathodoluminescence image which can be easily measured by a scanning electron microscope combined with a reflector and a photodetector. Since the cathodoluminescence image can be obtained with a higher resolution of 0.5 to 1 .mu.m in comparison with a photoluminescence image with a resolution of 10 to 100 .mu.m, the cathodoluminescence image can make clear the inhomogeneity of the wafers which are even homogeneous by observing photoluminescence images. GaAs single crystal has been often studied for a long time through its cathodoluminescence image. These studies reported that none of GaAs single crystals could provide uniform cathodoluminescence images. The inventors have also carried out measurements to determine the cathodoluminescence image on variously heat-treated single crystals in conventional manners. According to these measurements, some crystals could not provide completely uniform cathodoluminescence images. The inhomogeneity of a cathodoluminescence image can be caused by impurities and/or native defects such as EL2 inhomogeneously distributed in the crystal. This inhomogeneous distribution would result in variations in the threshold voltage Vth of FETs.
As one conventional method, an ingot of the single crystal has been annealed by two steps. This two step annealing method has however been proven that it has a demerit, that the density of microscopic defects; i.e., egg shape etch pits, revealed in the single crystal by AB etchant (Abrahams and Buiocchi etchant: 2lm H.sub.2 O+8 mg AgNO.sub.3 +1 g CrO.sub.3 +1 mlHF) is always high. Then the inventors have studied the relationship between the microscopic defect density revealed by AB etchant and FET properties. They found the fact that the threshold voltage, Vth, of FETs fluctuates so much that the threshold voltage can not be controlled within a specific voltage range when the microscopic defects are observed under the gate of the FETs.
As a result, the conventional heat-treatments after the single crystal growth step can not produce the crystal wafers possessing a uniform cathodoluminescence image and less microscopic defects revealed by the AB etchant. This will cause poor properties of the electronic devices formed on the wafers, and thus the yield in the electronic device manufacturing process will be decreased.